1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to dynamic random access memories (DRAMs) with cell structure including bit lines easily processed and a method of manufacturing such cell structure.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) type DRAM comprises memory cells each including a MOS transistor and a capacitor. As the integration of DRAM improves, an area of each capacitor of the DRAM will shrink that reduce amount of charges to be stored in the capacitor. This may cause errors (soft errors) to destroy the memory's contents.
To solve this problem, there has been proposed a method of forming storage nodes with polycrystalline silicon, etc., on a silicon substrate to expand the occupying area of each capacitor and increase capacitance, i.e., amount of charges to be stored in the capacitor.
This sort of DRAM is shown in FIGS. 1a to 1c, in which FIG. 1a is a plan view, FIG. 1b a sectional view taken along a line A--A' of FIG. 1a, and FIG. 1c a sectional view taken along a line B--B' of FIG. 1. The figures show cells of the DRAM corresponding to adjacent two bits.
In the figures, a numeral 101 is a p-type silicon substrate, and 105 an element separating insulation film. A storage node electrode 113 is made of, for instance, polycrystalline silicon. The storage node electrode 113 contacts the silicon substrate 101 through a storage node contact 112. The surface of the storage node electrode 113 is coated with a capacitor insulation film 114 on which a plate electrode 115 is deposited to form a MOS capacitor. Adjacent to the capacitor region, a MOS transistor is formed. Namely, a gate insulation film 109 is formed on then silicon substrate 101, and a gate electrode 110 is formed on the gate insulation film 109. With the gate electrode as a mask, impurity ions are implanted in the silicon substrate 101 to form n-type layers 107 which will be source and drain of the MOS transistor. The MOS capacitor and MOS transistor thus formed constitute a cell which is called a stacked capacitor cell.
In the stacked capacitor cell, the storage node electrode 113 extends over the element separating insulation film 105, and a stepped portion 113' of the storage node electrode 113 contributes to increase capacitance.
With this arrangement, the capacitance is several times larger than that of a planar structure DRAM. Accordingly, a memory cell occupying area of the capacitor may be reduced with no reduction in the amount of charges to be stored in the capacitor. Moreover, a diffusion layer existing at a storage node portion to collect charges generated by alpha rays is only the diffusion layer 107 located under the storage node electrode 113. Namely, the diffusion layer which may collect the charges is remarkably small, thus providing a soft-error-resistive cell structure.
However, this cell structure has some drawbacks. Since the cell structure is not planar, it is hard to process. The number of electrodes of each stacked capacitor cell is larger by one than that of a planar capacitor cell because the stacked capacitor cell stores charges at the storage node electrode 113 while the planar capacitor cell stores the charges on a silicon substrate. In the stacked capacitor cell, the upper a layer is located, the poorer its flatness. Therefore, the stacked capacitor cell is difficult to process with photolithography and etching techniques, and this difficulty may cause many open defects and short-circuit defects on the electrodes.
Stepped portions are formed between the storage node electrode 113, capacitor insulation film 114 and plate electrode 115 so that the upper surface of an interlayer film 116 is greatly distanced from the substrate 101. This makes processing a bit line 118 difficult, and adversely affects on the coating characteristics of metal of the bit line 118.
To improve integration of the DRAM, an area of the storage node electrode 113 shall be reduced. Then, to maintain a fixed capacitance of the capacitor, the thickness of the storage node electrode 113 shall be increased to increase a ratio of capacitance provided by the stepped portion 113'. This may further degrade the flatness of the cell structure.
To connect the bit line 118 with the substrate 101 through a bit line contact 107, the plate electrode 115 shall be processed within a limited space between an edge of the storage node electrode 113 and the bit line contact 117. Namely, the dimensional allowance for this process is small, to adversely affect integration. In addition, it is difficult to process the plate electrode 115 due to the large stepped portions formed by lower layers.
Further, the conventional stacked capacitor cell structure needs many heat treatment processes after the formation of the capacitor insulation film 114. If the capacitor insulation film 114 is formed of high dielectric materials, the heat treatments may adversely influence the capacitor insulation film 114.
As described in the above, DRAMs employing the conventional stacked capacitor cell structure are poor in flatness, difficult to process and incapable of integration.